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16 Mbit LPC Serial Flash
A Microchip Technology Company
SST49LF016C
Data Sheet
Design Considerations
SST recommends a high frequency 0.1 μF ceramic capacitor to be placed as close as possible
between V DD and V SS less than 1 cm away from the V DD pin of the device. Additionally, a low fre-
quency 4.7 μF electrolytic capacitor from V DD to V SS should be placed within 1 cm of the V DD pin. If you
use a socket for programming purposes add an additional 1-10 μF next to each socket. The RST# pin
must remain stable at V IH for the entire duration of an Erase operation. WP#/AAI must remain stable at
V IH for the entire duration of the Erase and Program operations for non-Boot Block sectors. To write
data to the top Boot Block sectors, the TBL# pin must also remain stable at V IH for the entire duration
of the Erase and Program operations.
Mode Selection
The SST49LF016C flash memory device operates in two distinct interface modes: the LPC mode and
the Auto Address Increment (AAI) mode. The WP#/AAI pin is used to set the interface mode selection.
The device is in AAI mode when the WP#/AAI pin is set to the Supervoltage V H (9±0.5V), and in the
LPC mode when the WP#/AAI is set to V IL /V IH. The mode selection must be configured prior to device
operation.
?2011 Silicon Storage Technology, Inc.
10
DS25029A
06/11
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